An application-specific integrated circuit (ASIC) is an integrated circuit (IC) customized for a specific use, instead of intended for general-purpose use. For example, a chip designed solely to run a cell phone is an ASIC. In contrast, the 7400 series and 4000 series integrated circuits are logic building blocks that can be wired together for use in many different applications. Intermediate between ASICs and standard products are application specific standard products (ASSPs).

As feature sizes have shrunk and design tools improved over the years, the maximum complexity (and hence functionality) possible in an ASIC has grown from 5,000 gates to over 100 million. Modern ASICs often include entire 32-bit processors, memory blocks including ROM, RAM, EEPROM, Flash and other large building blocks. Such an ASIC is often termed a SoC (System-on-a-chip). Designers of digital ASICs use a hardware description language (HDL), such as Verilog or VHDL, to describe the functionality of ASICs.

Field-programmable gate arrays (FPGA) are the modern day equivalent of 7400 series logic and a breadboard, containing programmable logic blocks and programmable interconnects that allow the same FPGA to be used in many different applications. For smaller designs and/or lower production volumes, FPGA's may be more cost effective than an ASIC design. The Non-recurring engineering cost (the cost to set up the factory to produce a specific ASIC) can run into the millions of dollars.

The general term application specific integrated circuit includes FPGAs, but most designers use ASIC only for non field programmable devices (e.g. standard cell or sea of gates) and make a distinction between ASIC and FPGAs.

ASIC-based Intrusion-prevention system (IPS) detect and block denial of service attacks; they have the processing power and the granularity to analyze the attacks and act like a circuit breaker in an automated way.

History

The initial ASICs used gate array technology. Ferranti produced perhaps the first gate-array, the ULA (Uncommitted Logic Array), around 1980. Customization occurred by varying the metal interconnect mask. ULAs had complexities of up to a few thousand gates. Later versions became more generalized, with different base dies customised by both metal and polysilicon layers. Some base dies include RAM elements.

Standard cell design

Main article: standard cell

In the mid 1980s a designer would choose an ASIC manufacturer and implement their design using the design tools available from the manufacturer. While third party design tools were available, there was not an effective link from the third party design tools to the layout and actual semiconductor process performance characteristics of the various ASIC manufacturers. Most designers ended up using factory specific tools to complete the implementation of their designs. A solution to this problem that also yielded a much higher density device was the implementation of Standard Cells. Every ASIC manufacturer could create functional blocks with known electrical characteristics, such as propagation delay, capacitance and inductance, that could also be represented in third party tools. Standard Cell design is the utilization of these functional blocks to achieve very high gate density and good electrical performance. Standard cell design fits between Gate Array and Full Custom design in terms of both its NRE (Non-Recurring Engineering) and recurring component cost.

By the late 1980s, logic synthesis tools became available. Such tools could compile HDL descriptions into a gate-level netlist. This enabled a style of design called standard-cell design. Standard-cell Integrated Circuits (ICs) are designed in the following conceptual stages, although these stages overlap significantly in practice.

These steps, implemented with a level of skill common in the industry, almost always produce a final device that correctly implements the original design, unless flaws are later introduced by the physical fabrication process.

A team of design engineers starts with a non-formal understanding of the required functions for a new ASIC, typically derived from Requirements analysis.

The design team constructs a description of an ASIC to achieve these goals using an HDL. This process is analogous to writing a computer program in a high-level language. This is typically called the RTL (Register transfer level) design.

Suitability for purpose is verified by functional verification. This may include such techniques as logic simulation, formal verification, emulation, or creating an equivalent pure software model (see Simics, for example). Each technique has advantages and disadvantages, and often several methods are used.

Logic synthesis transforms the RTL design into a large collection of lower-level constructs called standard cells. These constructs are taken from a standard-cell library consisting of pre-characterized collections of gates (such as 2 input nor, 2 input nand, inverters, etc.). The standard cells are typically specific to the planned manufacturer of the ASIC. The resulting collection of standard cells, plus the needed electrical connections between them, is called a gate-level netlist.

The gate-level netlist is next processed by a placement tool which places the standard cells onto a region representing the final ASIC. It attempts to find a placement of the standard cells, subject to a variety of specified constraints.

The routing tool takes the physical placement of the standard cells and uses the netlist to create the electrical connections between them. Since the search space is large, this process will produce a “sufficient” instead of “globally-optimal” solution. The output is a file that can be used to create a set of photomasks enabling a semiconductor fabrication facility (frequently called a 'fab') to produce physical ICs.

Given the final layout, circuit extraction computes the parasitic resistances and capacitances. In the case of a digital circuit, this will then be further mapped into delay information, from which the circuit performance can be estimated, typically by static timing analysis. This, and other final tests such as design rule checking and power analysis (collectively called signoff) are intended to insure that the device will function correctly over all extremes of the process, voltage and temperature. When this testing is complete the photomask information is released for chip fabrication.

These design steps (or flow) are also common to standard product design. The significant difference is that Standard Cell design uses the manufacturer's cell libraries that have been used in potentially hundreds of other design implementations and therefore are of much lower risk than full custom design. Standard Cells produce a design density that is cost effective, and they can also integrate IP cores and SRAM (Static Random Access Memory) effectively, unlike Gate Arrays.

Gate array design

Gate Array design is a manufacturing method in which the diffused layers, i.e. transistors and other active devices, are predefined and wafers containing such devices are held in stock prior to metallization, in other words, unconnected. The physical design process then defines the interconnections of the final device. For most ASIC manufacturers, this consists of from two to as many as five metal layers, each metal layer running parallel to the one below it. Non-recurring engineering costs are much lower as photo-lithographic masks are required only for the metal layers, and production cycles are much shorter as metallization is a comparatively quick process. It is also vital to the designer that minimal propagation delays can be achieved in ASICs versus the FPGA solutions available in the marketplace. Gate Array ASICs are always a compromise as mapping a given design onto what a manufacturer held as a stock wafer never gives 100% utilization. Often difficulties in routing the interconnect require migration onto a larger array device with consequent increase in the piece part price. These difficulties are often a result of the layout software used to develop the interconnect.

Pure, logic-only Gate Array Design is rarely implemented by circuit designers today, replaced almost completely by field programmable devices, such as FPGAs (Field Programmable Gate Arrays), that can be programmed by the user andthereforeoffer minimal tooling charges (Non-recurring engineering (NRE)), marginally increased piece part cost and comparable performance. Today Gate Arrays are evolving into Structured ASICs that consist of a large IP core like a processor, DSP unit, peripherals, standard interfaces, integrated memories SRAM, and a block of reconfigurable uncommited logic. This shift is largely because ASIC devices are capable of integrating such large blocks of system functionality and "system on a chip" requires far more than just logic blocks.

The term "Gate Array" is almost synonymous and interchangeable with the term "Semi-Custom". Which term you would use depends on who you are; if you are a process engineer, more likely than not you would use "Semi-Custom" whereas if you are a logic (or gate level) designer, "Gate-Array" would probably be your term of choice.

Full-custom design

Main article: full custom

By contrast, Full-Custom ASIC Design defines all the photo lithographic layers of the device. Full Custom Design is used for both ASIC design and for Standard Product design.

The benefits of Full-Custom Design typically include reduced area (and therefore recurring component cost), performance improvements and also the ability to integrate (include) analog components and other pre-designed (andthereforefully verified) components such as microprocessor cores that form a System-On-Chip. The disadvantages of Full-Custom can include increased manufacturing and design time, increased non-recurring engineering costs, more complexity in the Computer Aided Design (CAD) system and a much higher skill requirement on the part of the design team. However for digital only designs, "standard-cell" cell libraries together with modern CAD systems can offer considerable performance/cost benefits with low risk. Automated layout tools are quick and easy to use and also offer the possibility to "hand-tweak" or manually optimise any performance limiting aspect of the design.

Structured/platform design

Structured (also referred to as Platform) ASIC Design is an ambiguous expression, with different meanings in different contexts. This is a comparatively new term in the industry, which is why there is some variation in its definition. However, the basic premise of a Structured/Platform ASIC is that both manufacturing cycle time and design cycle time are reduced compared to cell-based ASIC by virtue of there being pre-defined metal layers (thus reducing manufacturing time) and pre-characterization of what is on the silicon (thus reducing design cycle time). One definition states that In a "structured ASIC" design, the logic mask-layers of a device are predefined by the ASIC vendor (or in some cases by a third party). Design differentiation and customization is achieved by creating custom metal layers that create custom connections between predefined lower-layer logic elements. "Structured ASIC" technology is seen as bridging the gap between field-programmable gate arrays and "standard-cell" ASIC designs. Because only a small number of chip layers must be custom-produced, "structured ASIC" designs have much smaller non-recurring expenditures (NRE) than "standard-cell" or "full-custom" chips, which require that a full mask set be produced for every design. This is effectively the same definition as a Gate Array.

What makes a Structured/Platform ASIC different from a gate array is that in a gate array the predefined metal layers serve to make manufacturing turnaround faster. In a Structured/Platform ASIC the predefined metallization is primarily to reduce cost of the mask sets and is also used to make the design cycle time significantly shorter as well. For example, in a cell-based or gate-array design the user often must design power, clock, and test structures themselves; these are predefined in most Structured/Platform ASICs and therefore can save time and expense for the designer compared to gate-array. Likewise, the design tools used for Structured/Platform ASIC can be substantially lower cost and easier (faster) to use than cell-based tools, because the tools do not have to perform all the functions that cell-based tools do. In some cases, the Structured/Platform ASIC vendor requires that customized tools for their device (for example, custom physical synthesis) be used, also allowing for the design to be brought into manufacturing more quickly. ChipX, Inc. and eAsic are examples of vendors offering this kind of Structured ASIC.

One other important aspect about Structured/Platform ASIC is that it allows IP that is common to certain applications or industry segments to be "built in", instead of "designed in". By building the IP directly into the architecture the designer can again save both time and money compared to designing IP into a cell-based ASIC.

The best advice is to read carefully how the vendor defines its specific Structured or Platform ASIC, as there are significant differences between vendors offering these devices.

The Altera technique of producing a structured cell ASIC where the cells are the same design as the FPGA, but the programmable routing is replaced with fixed wire interconnect is called HardCopy. These devices then do not need re-programming and can't be re-programmed as an FPGA.

The Xilinx technique of producing a customer specific FPGA, that is 30% - 70% less expensive than a standard FPGA and where the cells are the same as the FPGA but the programmable capability is removed , is called EasyPath.

Cell libraries, IP-based design, hard and soft macros

Cell Libraries of logical primitives are typically provided by the device manufacturer as part of the service. Although they will incur no extra cost, their release will be covered by the terms of a non disclosure agreement (NDA) and they will be regarded as intellectual property by the manufacturer. Usually their physical design will be pre-defined as so they could be termed hard macros.

But what most engineers understand as "intellectual property" are IP cores, designs purchased from a third party as sub-components of a larger ASIC. They may be provided as an HDL description (often termed a soft macro), or as a fully routed design that could be printed directly onto an ASIC's mask (often termed a hard macro). Many organizations now sell such pre-designed IP, and larger organizations may have an entire department or division to produce such IP for the rest of the organization. For example, one can purchase CPUs, ethernet, USB or telephone interfaces. Indeed, the wide range of functions now available is a significant factor in the phenomenal increase in electronics in the late 1990s and early 2000s; as intellectual property takes a lot of time and investment to create, its re-use and further development cuts product cycle times dramatically and creates better products.

Soft Macros are often process independent; i.e., they can be fabricated on a wide range of manufacturing processes and indeed different manufacturers.

Hard Macros are process limited and typically further design effort must be invested to migrate (port) to a different process or manufacturer.

Multi-project wafers

Some manufacturers offer Multi-Project Wafers (MPW) as a method of obtaing low cost prototypes. Often called shuttles, these MPW, containing several designs, run at regular, scheduled intervals on a "cut and go" basis, typically with very little liability on the part of the manufacturer. The contract involves the assembly and packaging of a handful of devices. The service typically involves the supply of a physical design data base i.e. masking information or Pattern Generation (PG) tape. The manufacturer is often referred to as a "silicon foundry" due to the low involvement it has in the process. See also Multi Project Chip.

ASIC manufacturers (foundries)

Chartered

cPackets

eInfochips

Fujitsu

Freescale

IBM

Infineon Technologies

MHS Electronics

MOSIS

NVIDIA

NEC

Samsung

SMIC

Texas Instruments

TSMC

UMC

X-Fab